Who am I?

Personal Details

Utkarsh Mathur
  • Name: Utkarsh Mathur
  • Date of birth: 27 January 1994
  • Phone: +1 (919)-349-6756
  • Location: Raleigh, NC
  • Email: u7karsh@yahoo.co.in
  • Latest CV:   
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About Me

I am a Master's student pursuing Electrical and Computer Engineering at NC State University, Raleigh.

I have worked at Cadence Design Systems for two years in the field of Verification IP (VIP) for protocols like HDMI, I2C, MHL and USB type-C.

I am currently researching in the field of computer architecture with special interests in high-performance microarchitecture, General Purpose Computation on Graphics Processors (GPGPU), and architectural support for security.

What I'm best at

Skills & Knowledge

Software


Languages

C/C++, CUDA, Verilog, SystemVerilog, Python, Assembly for RISC-V, Java, PHP, HTML, SQL, CQL

Packages

GPGPU-sim, 721sim (cycle-accurate RISC-V superscalar simulator), MATLAB, ModelSim, Synopsys Design Vision, LaTeX

Methodologies

UVM ( Universal Verification Methodology )

Version Control

ClearCase, Perforce, GIT.

Operating Systems

Unix/Linux ❤, Windows.

Hardware


FPGA

Papilio Pro (Spartan 6)

Processors

TMS320F2812, 8051

Controllers

dsPIC30 and dsPIC33 family, and ATmega328

Development Boards

Arduino, Raspberry Pi and Galileo board.

My Professional Background

Work Experience

2018May - Present

NC State University

Raleigh

Research Assistant

Description

  • Architectural support for mitigating timing based side channel attacks on GPUs under Prof. Huiyang Zhou
  • High performance micro-architectural support for load latency hiding in modern superscalar CPUs under Prof. Eric Rotenberg

2015October - 2017July

Cadence Design Systems

Noida

R&D Engineer

Description

  • Development in Verification IP for the protocols HDMI, MHL & I2c
  • Co-created a component-based methodology with the aim to have more scalable and flexible architecture of Verification IPs and reduced time to market
  • Created features like Consumer Electronics Control (CEC) Physical Layer, adDDC from scratch

2015July - 2015October

Cadence Design Systems

Noida

R&D Intern at Cadence Design Systems, Noida for HDMI VIP

Description

  • Learnt various methodologies and trained in tools like ClearCase for Code Version Control
  • Tested HDMI verification IP and fixed major performance-related bugs
Click to browse through more Work Experience

2014May - 2014August

ADRDE

(Defence R&D Organization)

Intern

Description

  • Developed Data Logger using BL2120 SBC to replace their old firmware and increased recording time by a factor of 10
  • Designed schematic layout for data logging systems using dsPIC33F microcontroller for analyzing data recorded by various sensors during free fall to improve parachute designs
  • Invented a model for non-contact distance measurement of objects using Image Processing to help them determine terminal velocity of freely falling payloads

2014March - 2014April

RoboVito

Instructor

Description

  • Taught undergraduate level image processing for Robovito. Managed responsibility for lectures, workshops, and project

2013June - 2013July

NaMPET Laboratory
IIT Kanpur

Summer Intern

Description

  • Developed a software suite in assembly language for the DSP processor TMS320F2812 & incorporated a package of routines to implement any filter of Order 2
  • Enabled production of 50Hz three phase sinusoids with various control mechanisms for consistent voltage

My latest work

Projects


2018March - 2018May

Load Latency Hiding using Load Slice Buffer (LSB) and Load Value Prediction

Description

  • L2 miss penalty clogs the issue queue and prevents execution of independent instructions in the instruction window. Also, if this load reaches head of ROB, it stalls the retirement. We proposed to fake-retire the load, so that other independent instruction can continue to retire and give an illusion of continual flow.
  • Proposed and implemented a micro-arch for continual flow of instructions during retirement stall on L2 miss at head of ROB
  • Implemented LSB in 721sim (cycle-accurate superscalar simulator) to maintain fake-retired load dependent instructions
  • Implemented re-insertion of the instructions in slice to issue queue on load value misprediction
  • Implemented hierarchical store queue with membership test buffer (MTB) to prevent it from becoming a cycle time bottleneck

2018February - 2018May

Multipath Execution for Divergent Control Flow in GPUs

Description

  • The current SIMT stack approach serialize the execution of divergent control flow. We implemented a technique proposed by ElTantawy et. al. (A scalable multi-path microarchitecture for efficient GPU control flow), which allows interleaved execution of divergent paths.
  • Implemented split table and reconvergence table in GPGPU-sim to allow interleaved execution of divergent paths
  • Modified scoreboard logic to handle dependencies from diverged paths correctly

2018February - 2018April

Pipelined LC3 Microcontroller Functional Verification

Description

  • Implemented a layered verification model for LC3 microcontroller in SystemVerilog, including sequencer, driver, monitor, and environment
  • The package included a coverage plan and several test cases for functional completeness and correctness
GitHub: https://github.com/u7karsh/745_lc3_verif

2017November - 2017December

Dynamic Instruction Scheduling

Description

  • Developed a simulator for an out-of-order superscalar processor based on Tomasulo‚Äôs algorithm that fetches, dispatches, and issues N instructions per cycle with integrated two level caches. Perfect branch prediction was assumed
GitHub: https://github.com/u7karsh/dynamic_scheduler_ece563

2017October - 2017October

Synthesizable Convolutional Neural Network

Description

  • Developed a synthesizable Verilog design for two staged convolutional neural network arithmetic. Design generates 8-bit output vectors for object classification
  • Two parametrized architectures were proposed and developed with one being throughput and other being area oriented.
GitHub: https://github.com/u7karsh/cnn_ece564

2017September - 2017October

Branch Predictor and Cache Simulator

Description

  • Developed a generic cache simulator for WTWNA, WTWA and WBWA policies which could be used to instantiate any level of memory hierarchy with the option to augment victim cache. Replacement policies like LRU, LFU and LRFU were also incorporated
  • Worked on a cache simulator for MESI, MOESI and MSI cache coherence protocols
  • Developed a simulator for branch predictor with different configurations like GShare, BiModal, Hybrid with an option to add BTB
GitHub: https://github.com/u7karsh/cache_simulator_ece563
https://github.com/u7karsh/branch_predictor_ece563

2015January - 2015May

Reconfigurable computing using Field Programmable Gate Array

Description

  • Built a computer System on Chip (SoC) on Papilio Pro (Spartan 6) based on Zilog 80 core with 4KB paged Memory Management Unit (64KB virtual, 64MB physical address space) along with 8MB SDRAM with 16KB 4-way associative cache and communication protocol Universal Asynchronous Receiver Transmitter (UART)
  • Created several programs in assembly to demonstrate features like user input using UART module, arithmetic operations, etc.
Click to browse through more Projects

2015March - 2015May

Cryptex

Description

  • Created a hardware cryptographic tool using C, Java, Python to securely upload and download files on a cloud
  • To ensure data security & integrity, system used sessions keys and authentication tokens generated from the hardware using Milenage algorithm that is used in GSM

2015January - 2015March

FPGA Place and Route

Description

  • Developed open source tool chain using C++ for implementing a place & route mechanism for iCE40 FPGA
  • Tool chain used already existing FPGA synthesizer (YOSYS) to develop a fully open source FPGA compilation flow

2014August - 2014December

Hardware Signal Processing Toolbox

Description

  • Designed a low cost (~30$) tool using dsPIC33EP microcontroller for facilitating 3-channel hardware signal processing (up to 1.0MHz bandwidth) that interfaced with MATLAB & JAVA

2014October - 2014December

Pose Invariant Face Recognition

Description

  • Dataset of 35 males was created manually by taking 5 photographs of each male in different poses
  • Features were selected using the embedded method for deep learning
  • Images were cropped & pre-processed using Gabor filter & Histogram Equalization after being converted to gray scale
  • Keeping all the frontal face images in test set, linear Support Vector Machine achieved an accuracy of 74%

2014May - 2014July

Bifrost

Description

  • Centralized & digitized the fee collection data of Jaypee Youth Club through deployment of a central CentOS-based TCP server, that hosted a JAVA-based GUI application for fee collection, receipt printing & uploading data to the server on a channel securely using Python
  • An automated email to every fee depositor as a receipt confirmation was an added feature

2013July - 2014May

Micro Electro Mechanical Systems (MEMS)

Description

  • Modelled a Cantilever-based clamped free resonators with Magnetostatic actuation, Piezoresistive detection & Electrostatic actuation, electrostatic detection using Verilog A at the Centre for Microelectromechanical Systems (MEMS) design funded by the National Program on Micro & Smart Systems (NPMASS) initiated by Aeronautical Development Agency (ADA), Govt. of India.

2013August - 2013September

Grid Solving Robot

Description

  • Robot capable of solving a grid by finding & traversing the shortest path using Dijkstra's algorithm from one node to another without crossing the blocked/restricted nodes
  • Robot had the capability to pick objects from target node autonomously

2013May - 2014September

Websites

Description

  1. Impressions 2013 and 2014: Designed official website of techno-cultural festival at JIIT, Noida
  2. Jaypee Model United Nations 2014: Designed official website for JMUN 2014
  3. ICSC 2013 and 2015: Designed payment gateway for International Conference on Signal Processing and Communication using JavaServer Pages.

Website link: http://u7karsh.com/projects

2013April - 2013May

Foot Mouse

Description

  • Developed a system using an accelerometer interfaced with a microcontroller that could easily be attached to a person's shoe
  • Used this module & C++ interface to control the location of mouse pointer on the Windows platform & performed a left/right click operation
  • Versatile for games like FIFA & Pro Evolution Soccer

2012June - 2012August

OpenCV-Based Marker Detection Library

Description

  • A robust intensity invariant marker detection framework was developed using OpenCV in C++ to train multiple markers & use it to detect & obtain the Pose Matrices of all markers in a video stream
  • The Pose Matrix could then be used in a variety of augmented reality application

My research work?

Publications



Journals

Sharma, R., Mathur, U., Srivastava, N., "Angular Skew Correction Algorithm for Handwritten Hindi Text", International Journal of Advance Computer Research; Jun2013, Vol. 3 Issue 2, p43.[Impact factor: 1.863]

Conferences

Mathur, U., Sharma, R., Srivastava, N., "Script independent angular skew detection and correction algorithms", 2013 International Conference on Signal Processing and Communication (ICSC-2013), IEEE. pp. 466-469, 12-14 Dec. 2013. DOI: 10.1109/ICSPCom.2013.6719835. [IEEE Xplore, SCOPUS]

What have I acheived?

Honour's and Awards

AISSCE

2009
Merit Certificate holder from CBSE (Science) for being in the top 0.1% of students who appeared in All India Senior School Certificate Examination (AISSCE 2009)

HoverOn

January 2014
Secured 1st prize in HoverOn, a line following hovercraft event at Asia's largest Science and Technical Festival, IIT Bombay, 2014

Click here to browse through more Awards

Magneto

January 2014
Finalists in Magneto, a gesture controlled robotic event at Asia's largest Science and Technical Festival, IIT Bombay, 2014

Trailblazer

March 2013
Awarded 2nd prize in Trailblazer, a manual + autonomous line following bot event, Impressions JIIT, 2013

RoboWars

September 2012
Received 1st prize in RoboWars, Neuron Malaviya National Institute Technology(MNIT), 2012

Line Follower

September 2012
Recipient of 2nd prize in Line Follower, Neuron MNIT, 2012

Rescuer

September 2012
Awarded 3rd prize in Rescuer, a manual + autonomous grid solving bot event, Neuron MNIT, 2012

Connexions

March 2012
Secured 2nd prize in Connexions, a manual + autonomous line following bot event, Impressions JIIT, 2012